MC68302RC16C

integrated multiprotocol processor (IMP), 132-PGA, -0.3 to + 7.0 V, Motorola

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Price:: US $16.00~30.00 / piece [Get Latest Price]

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	US $16.00~30.00

PartNumber:: MC68302RC16C

Brand:: Motorola, Inc - Motorola | Pack: PGA | D/C: 04+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-09-20

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Part Number:MC68302RC16C
US $16.00 - 30.00
A50L-0001-0175

US $100.00 - 100.00 / Piece
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CM2030-A0TR

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Product Summary

The MC68302RC16C integrated multiprotocol processor (IMP) is a very large-scale integration (VLSI) device incorporating the main building blocks needed for the design of a wide variety of controllers. The device is especially suitable to applications in the communications industry. The IMP MC68302RC16C is the first device to offer the benefits of a closely coupled, industry-standard M68000 microprocessor core and a flexible communications architecture. The IMP MC68302RC16C may be configured to support a number of popular industry interfaces, including those for the Integrated Services Digital Network (ISDN) basic rate and terminal adaptor applications. Concurrent operation of different protocols is easily achieved through a combination of architectural and programmable features. Data concentrators, line cards, modems, bridges, and gateways are examples of suitable applications for this device. The IMP MC68302RC16C is a high-density complementary metal-oxide semiconductor (HCMOS) device consisting of an M68000 microprocessor core, a system integration block (SIB), and a communications processor (CP).

Parametrics

MC68302RC16C absolute maximum ratings: (1)Supply Voltage VDD: -0.3 to + 7.0 V; (2)Input Voltage Vin: -0.3 to + 7.0 V; (3)Operating Temperature Range TA: 0 to 70 ℃; (4)Storage Temperature Range Tstg: -55 to + 150 ℃.

Features

MC68302RC16C features: (1)Independent Direct Memory Access (IDMA) Controller with Three Handshake Signals: DREQ, DACK, and DONE.; (2)Interrupt Controller with Two Modes of Operation; (3)Parallel Input/Output (I/O) Ports, Some with Interrupt Capability; (4)On-Chip 1152-Byte Dual-Port RAM; (5)Three Timers Including a Watchdog Timer; (6)Four Programmable Chip-Select Lines with Wait-State Generator Logic; (7)Programmable Address Mapping of the Dual-Port RAM and IMP Registers; (8)On-Chip Clock Generator with Output Signal.